The invention relates generally to a flash memory device, and more particularly to, an address buffer in a flash memory into which a flash cell is inserted, capable of selecting specific sectors in a high integrated core product.
In general, unlike a general DRAM or SRAM, a flash memory requires a product strategy to satisfy various market needs of flexible manufacturing system. It can be accomplished through product development in a short period of time. To meet this market need, the conventional method of developing a flash memory is to manufacture a low cost product by verifying the technology through a core product and then acquiring an additional development schedule.
As shown in FIG. 1, in the conventional address buffer, the address terminals A0xcx9cA18 externally inputted for programming or erase are connected to one ends of the NAND gates NA0xcx9cNA18, respectively. Then, the input ends on the other ends of the NAND gates NA0xcx9cNA18 are connected to each other and are then connected to the output ends of the inverter 10 that is connected to the output terminal of the chip enable /CE. Also, the output ends of the NAND gates NA0xcx9cNA18 are each connected to the inverters NT0xcx9cNT18, wherein the outputs ends of respective inverters NT0xcx9cNT18 are connected to an internal circuit to output an internal address IA0xcx9cIA18.
The operation of the conventional address buffer will be now explained below.
The addresses A0xcx9cA18 externally inputted are each connected to one ends of the NAND gates. Also, the chip enable /CE is inputted to the inverter 10. Accordingly, if a LOW signal is inputted to the chip enable /CE, the inverter 10 outputs HIGH signals to the other input ends of the NAND gates NA0xcx9cNA18, respectively.
Each of the NAND gates NA0xcx9cNA18 the output ends of which are connected the inverter performs the same operation with the AND gates. Thus, if the above-mentioned the chip enable /CE is at LOW signal, respective NAND gates operates depending on the addresses A0xcx9cA18 which are inputted to one ends of the NAND gates. That is, if the address A0 is at HIGH signal, the NAND gate NA0 output a LOW signal. Therefore, the inverter NT0 outputs a HIGH signal. Also, if the address A0 is at LOW signal, the NAND gate NA0 outputs a HIGH signal and the inverter NT0 outputs a LOW signal. In other words, if the chip enable /CE is at LOW signal, the address buffer transfers the addresses A0xcx9cA18 to the internal addresses IA0xcx9cIA18 intact.
However, conventionally, if any of sectors in the memory block is damaged as a result of testing a completed memory, the damaged memory itself must be discarded. Due to this, there are problems that the throughput in the process is degraded and the const of the product is increased.
It is therefore an object of the present invention to provide an address buffer in a flash memory including a non-volatile sector select code cell by which a given sector can be selected in order to use a normal sector, by disabling a memory sector having defects generated in a high integrated corer product.
In order to accomplish the above object, an address buffer in a flash memory according to the present invention is characterized in that it includes a buffer section for buffering external addresses; a code storage section for storing a code to select a memory sector in the flash memory; and a setting section for outputting internal addresses selecting said memory sector, by using the code outputted from said code storage section and sector select addresses among said external addresses.
The buffer section comprises a plurality of NAND gates to one end of which is input said external address and to the other end of which is input an inverted chip enable signal; and a plurality of inverters each connected to the output ends of said NAND gates, respectively.
The code storage section comprises first and second flash cells for storing codes selecting the memory sector, depending on program/erase state.
The setting section comprises a first PMOS transistor and a third PMOS transistor to the gate of which is inputted a chip enable signal; a second PMOS transistor connected between said first PMOS transistor and a first flash cell ; a fourth PMOS transistor connected between said third PMOS transistor and a second flash cell; first and second inverters connected between said fourth PMOS transistor and said second flash cell; first and second transmission gates that are turned on and off by means of the output signal from said first and second inverters; third and fourth inverters connected between said second PMOS transistor and said first flash cell; a third transmission gate that is turned on and off by means of the output signal from said fourth inverter; and a NAND gate one end of which inputs the signal passed through said second transmission gate and the other input end of which inputs the output signal from said third inverter to thus output the internal address.
The first transmission gate outputs the output signal of any one of the inverters to the internal address. The third transmission gate is turned on and off depending on the output signal of said fourth inverter to thus connect the output ends of said first transmission gate and said second transmission gate.